The present invention relates to apparatus and a method for determining the parity of an optical binary word, the binary word being represented by a sequence of W optical bit slots.
In the field of all optical processing, optical signal streams are used for data processing applications. These optical streams consist of an optical pulse train that is divided into a series of bit slots. Each bit slot, which has a predetermined length within the pulse train, represents a single bit of data, with the presence or absence of an optical pulse within a bit slot representing complementary logical states.
Thus, for example, the presence of a pulse may represent a binary xe2x80x9c1xe2x80x9d, whilst the absence of an optical pulse may represent a binary xe2x80x9c0xe2x80x9d, or vice versa. In this specification, therefore, we use the terminology xe2x80x9coptical binary wordxe2x80x9d to mean a binary word represented optically in this manner.
One of the basic optical processing applications which is required is the ability to determine the parity of an optical binary word. The parity of an optical binary word represents the presence of optical pulses in the bit slots of the binary word. The parity is represented in the form of a parity word whose logical state changes if there is an optical pulse in the corresponding bit slot of the binary word.
Such parity words are frequently used in error checking and correction systems. In such systems, a check sum is provided within the packet which is compared to a parity word determined by counting the parity of bit slots within the data packet. Any difference in the result of this comparison then indicates that an error has occurred during transfer of the packet such that either correction or re-transmission of the data packet is required.
A further use of parity words is the identification of rogue packets on a data network. In networks in which data is transferred in data packets, it is a common problem that incorrectly addressed packets continue to propagate around the network indefinitely. One possible way around this problem is to only use addresses with even (or odd) parity and then eliminate all packets which have an address of the opposite parity. The parity of the address, which is contained in a packet header, is then determined from the parity word corresponding to the packet header, allowing all packets which have an address of the incorrect parity to be eliminated.
According to a first aspect of the present invention, we provide parity determining apparatus for determining the parity of a binary word, the binary word being represented by a sequence of W optical bit slots, each bit slot defining a respective one of first and second complementary logical states, the apparatus comprising an input pulse stream generator which generates copies of the W bit slot word; a combining means which receives first and second binary words, offsets the first and second binary words by one bit slot and combines the relatively offset first and second binary words to form a combination word; and, means for applying P times in succession a copy of the W bit slot binary word and the previously generated combination word to combining means, whereby the parity of the first P bit slots of the W bit slot word are given by the first P bit slots of the resultant combination word, the first combination word comprising a sequence of optical bit slots having the same logical state.
According to a second aspect of the invention, we provide a method for determining the parity of a binary word, the binary word being represented by a sequence of W optical bit slots, each bit slot defining a respective one of first and second complementary logical states, the method comprising generating copies of the W bit slot word; forming a combination word from first and second binary words by offsetting the first and second binary words by one bit slot and combining the relatively offset first and second binary words; and, forming the combination word P times in succession from a copy of the W bit slot binary word and the previously generated combination word, whereby the parity of the first P bit slots of the W bit slot word are given by the first P bit slots of the resultant combination word, the first combination word comprising a sequence of optical bit slots having the same logical state.
We have designed a method and apparatus for determining the parity of a binary word. The parity of the binary word is determined for each bit slot of the binary word by combining a copy of the binary word with a copy of the binary word offset by one bit slot, to form a combination word.
The combination word is then offset by a single bit slot and again combined with a copy of the binary word. This is then repeated with the newly formed combination word being offset and combined with a copy of the binary word. If P different copies of the original binary word are utilised in the combinations, the final combination word generated will show the parity of the first P bit slots of the original word.
Accordingly the present invention provides a method and apparatus for determining the parity of an all optical binary word using only optical processing. This is in contrast to systems of the prior art which require non-optical processing in order to successfully determine the parity of data words. The use of such non-optical techniques results in a greater processing time and overly complicated apparatus.
Preferably, the input pulse stream generator generates an input optical pulse stream comprising the W optical bit slot word repeated at intervals of L bit slots.
Preferably, the combining means comprises an optical combiner having first and second combiner inputs, and a combiner output which generates a combined optical signal stream representing the combination of optical bit slots applied to the first and second combiner inputs respectively; and, an L+1 bit slot delay line, wherein the combiner output is coupled to the second combiner input via the L+1 bit slot delay line, and wherein the input optical pulse stream is applied to the first optical combiner input.
Alternatively an Lxe2x88x921 bit slot delay line could be used instead of the L+1 bit slot delay line. This is due to the requirement being that the W bit slot binary word and the combination binary word are offset by a single bit slot, the order of offset being irrelevant.
Whereas the above system using a single optical combiner uses feedback to achieve the repeated combination of the combination word and a copy of the binary word, it is also possible to use multiple optical combiners, with the output of one combiner coupled to the second input of a subsequent xe2x80x9cdownstreamxe2x80x9d combiner. By applying copies of the W bit slot word to the first input of the subsequent xe2x80x9cdownstreamxe2x80x9d combiners at the appropriate times, the parity word can be determined.
In order that timing be maintained, it is necessary for the copy of the W bit slot word to arrive offset by one bit slot with respect to the copy of the combination word. The offset may be achieved by having the N bit slot word arrive one bit slot before or one bit slot after the combination word. This could be achieved by supplying the input optical pulse stream comprising the W optical bit slot word repeated at intervals of L bit slots, to the first combiner input of each combiner. An L+1 bit slot delay line or alternatively an Lxe2x88x921 bit slot delay line is then located between the output of one combiner and the second input of the subsequent downstream combiner thereby introducing the one bit slot offset.
The use of the W bit slot word repeated at intervals of L bit slots in conjunction with either the L+1 or Lxe2x88x921 bit slot delay line is particularly advantageous as it allows the single bit slot offset to be achieved without the need for a single bit slot delay, which is difficult to achieve at high bit flow rates.
For ease of discussion, the remainder of the specification will discuss the example in which the W bit slot word arrives prior to the combination word. Accordingly, all the examples use an L+1 bit slot delay line, although it will be realised that an Lxe2x88x921 bit slot delay line could be used.
Typically the combining means includes an optical pulse source which generates optical pulses in successive bit slots, each optical pulse representing a logical state and, an all optical non-linear gate. These are used to ensure the combination signal stream generated by the combiner does not have more than one optical pulse in any bit slot.
Typically, the non-linear gate comprises a gate input coupled to the optical pulse source, a gate output, coupled to the L+1 bit slot delay line, which generates a gate output stream, and, a gate switching input coupled to the combiner output. In this case the application of a switching signal to the gate switching input selectively switches a connection between the gate input and the gate output so as to change the logical state of the gate output stream for a time interval corresponding to a single bit slot. However, any suitable non-linear gate could be used.
If the above mentioned non-linear gate is used, the combined optical signal stream acts as a series of switching signals such that the gate output stream is a copy of the combined signal stream.
Preferably the input pulse stream generator comprises an optical word generator which generates the W bit slot word, and, an L bit regenerative memory having a memory word input which is coupled to the optical word generator to receive the W bit slot word to be stored, and a memory word output which generates the input optical pulse stream. The regenerative memory provides a simple method of reliably generating a repeating optical bit slot sequence from a single original copy, without the need for having additional copies of the original word.
Typically the apparatus also includes an optical pulse source which generates optical pulses in successive bit slots, the L bit regenerative memory having an input coupled to the optical pulse source which receives the generated optical pulses. However, alternative pulse stream sources, such as a window generator may be used to produce optical signal streams lacking optical bit slots. Such signal streams can be used to reset the memory as required.
Although a system in which L=0 could be implemented, this would require the production of a bit slot delay line having a single bit slot delay which is difficult to achieve at high bit flow rates. Accordingly, it is preferable that Lxe2x89xa7W.
To further improve functioning of the device and increase the number of bit slots of the W bit slot binary word for which the parity can be determined, it is preferable that when an L+1 bit slot delay line is used Lxe2x89xa7W+Pxe2x88x922 and that when an Lxe2x88x921 bit slot delay line is used Lxe2x89xa7W+Pxe2x88x921. In general however, L will be much larger than P or W and this allows the parity word to recirculate in the feedback loop, formed by the combining means and the L+1 (or Lxe2x88x921) bit slot delay line, without the parity being rendered incorrect due to combination with a subsequently input W bit slot binary word.
Typically the switching signals used to switch the non-linear gate are a single optical pulse in a bit slot.
Typically a bit slot having the second logical state contains a single optical pulse.
Typically, the first combination word comprises a sequence of optical bit slots having the first logical state.